Difference between revisions of "Instruction Set/divRemu"

From Mill Computing Wiki
Jump to: navigation, search
m (Protected "Instruction Set/divRemu": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
(3 intermediate revisions by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:divRemu}}
 
{{DISPLAYTITLE:divRemu}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
−
'''native on:''' [[Assembly|none]]<br />
+
'''native on:''' [[Cores/Silver|Silver]] <br />
 
</div>
 
</div>
  
 
Unsigned integer division for quotient and remainder.
 
Unsigned integer division for quotient and remainder.
 +
 +
<b>related operations:</b> [[Instruction_Set/divu|divu]], [[Instruction_Set/remu|remu]], [[Instruction_Set/rdivu|rdivu]], [[Instruction_Set/rootu|rootu]], [[Instruction_Set/rrootu|rrootu]]
  
 
----
 
----
Line 11:Line 13:
 
</div>
 
</div>
 
<br />
 
<br />
 +
 +
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 +
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 +
|-
 +
| [[Cores/Silver/Encoding#divRemu|Silver]] || E0 ||
 +
|}
  
 
----
 
----
Line 17:Line 25:
 
</div>
 
</div>
 
<br />
 
<br />
 +
 +
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 +
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 +
|-
 +
| [[Cores/Silver/Encoding#divRemu|Silver]] || E0 ||
 +
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:04, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   that produces condition codes

native on: Silver

Unsigned integer division for quotient and remainder.

related operations: divu, remu, rdivu, rootu, rrootu

divRemu(u x, u y) → u r0, u r1

operands: like DivRem [xx:xx]


Core In Slots Latencies
Silver E0

divRemu(u x, imm y) → u r0, u r1

operands: like DivRem [xx:xx]


Core In Slots Latencies
Silver E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/divRemu&oldid=4913"