Difference between revisions of "Instruction Set/narrowdn"
From Mill Computing Wiki
| (2 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:narrowdn}} | {{DISPLAYTITLE:narrowdn}} | ||
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Rounding|and rounds toward negative infinity]]<br /> | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Rounding|and rounds toward negative infinity]]<br /> | ||
| − | '''native on:''' [[ | + | '''native on:''' [[Assembly|none]]<br /> |
</div> | </div> | ||
| − | + | Half the width of a decimal float value. Rounding towards negative infinity. | |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | Can produce the [http://en.wikipedia.org/wiki/IEEE_floating_point IEEE 754] 32bit decimal float interchange format. | |
| − | + | ||
| − | + | This is not a [[Speculable]] operation. The reason for this is the impossibility to fit all of the [[NaR]] payload into values smaller than 32bit. | |
| − | + | Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. | |
| − | + | If narrowing should prove a big bottleneck this can be revisited. | |
| − | + | ||
| − | + | ||
---- | ---- | ||
| Line 25: | Line 18: | ||
<br /> | <br /> | ||
| − | + | ---- | |
| − | + | <code style="font-size:130%"><b style="color:#050">narrowdn</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) → [[Domains#d|d]] r<sub>0</sub></code> | |
| − | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrowd|like Narrowd [dd:½d]]] | |
| − | + | </div> | |
| − | + | <br /> | |
| − | + | ||
| − | + | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 13:26, 23 February 2021
realizing exu stream exu block compute phase operation in the decimal floating point value domain and rounds toward negative infinity
native on: none
Half the width of a decimal float value. Rounding towards negative infinity.
Can produce the IEEE 754 32bit decimal float interchange format.
This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.
operands: like Narrowvd [DD:½D]
narrowdn(d op0, width width0) → d r0
operands: like Narrowd [dd:½d]
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
