Difference between revisions of "Instruction Set/neqd"

Latest revision as of 14:08, 23 February 2021

native on: none

Decimal float inequality comparison. When one of the operands is a NaN, a floating point invalid NaR is produced as the result.

related operations: neqdx

neqd(d x, d y) → d r₀

operands: like Addd [dd:d]

@@ Line 1: / Line 1: @@
 {{DISPLAYTITLE:neqd}}
-<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp;<br />
+<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp;<br />
-'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
+'''native on:''' [[Assembly|none]]<br />
 </div>
@@ Line 14: / Line 14: @@
 </div>
 <br />
-{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
-! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
-|-
-| [[Cores/Decimal8/Encoding#neqd|Decimal8]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
-|-
-| [[Cores/Decimal16/Encoding#neqd|Decimal16]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
-|}
 [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]