Difference between revisions of "Instruction Set/set"

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{{DISPLAYTITLE:set}}
 
{{DISPLAYTITLE:set}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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Set a single indexed bit.
 
Set a single indexed bit.
  
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<b>related operations:</b> [[Instruction_Set/clear|clear]], [[Instruction_Set/test|test]]  
+
<b>related operations:</b> [[Instruction_Set/clear|clear]], [[Instruction_Set/flip|flip]], [[Instruction_Set/test|test]]
  
 
----
 
----
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#set|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#set|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#set|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#set|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#set|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#set|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#set|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#set|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#set|Decimal8]] || E0 E1 E2 E3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#set|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#set|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#set|Tin]] || E0 ||  
−
|-
+
−
| [[Cores/Copper/Encoding#set|Copper]] || E0 E1 || 1
+
−
|-
+
−
| [[Cores/Silver/Encoding#set|Silver]] || E0 E1 E2 E3 || 1
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#set|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Copper/Encoding#set|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#set|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#set|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#set|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Gold/Encoding#set|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:56, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Set a single indexed bit.

related operations: clear, flip, test

set(op x, bit bit) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

set(op x, n bit) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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