Difference between revisions of "Instruction Set/merge"

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{{DISPLAYTITLE:merge}}
 
{{DISPLAYTITLE:merge}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
bitwise merge
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Bitwise merge.
 +
 
 +
It works like a multiplex: the bits in the mask operand decide whether the corresponding bit of the result is taken from op0 or op1.<br />
 +
Or explained differently: it does what [[Instruction_Set/pick|pick]] does on the operand level on the bit level.
 +
 
 +
----
 +
<code style="font-size:130%"><b style="color:#050">merge</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">op0</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
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</div>
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<br />
 +
 
 +
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 +
|-
 +
| [[Cores/Tin/Encoding#merge|Tin]] || E0 || 1
 +
|-
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| [[Cores/Copper/Encoding#merge|Copper]] || E0 || 1
 +
|-
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| [[Cores/Silver/Encoding#merge|Silver]] || E0 E1 E2 E3 || 1
 +
|-
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| [[Cores/Gold/Encoding#merge|Gold]] || E0 || 1
 +
|}
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">merge</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">mask</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">bits0</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops  
 
<code style="font-size:130%"><b style="color:#050">merge</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">mask</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">bits0</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#merge|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#merge|Tin]] || E0 ||  
|-
+
| [[Cores/Copper/Encoding#merge|Copper]] || E0 E1 || 1
+
|-
+
| [[Cores/Silver/Encoding#merge|Silver]] || E0 E1 E2 E3 || 1
+
 
|-
 
|-
| [[Cores/Gold/Encoding#merge|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Copper/Encoding#merge|Copper]] || E0 ||  
 
|-
 
|-
| [[Cores/Decimal8/Encoding#merge|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#merge|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
| [[Cores/Decimal16/Encoding#merge|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Gold/Encoding#merge|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:25, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Bitwise merge.

It works like a multiplex: the bits in the mask operand decide whether the corresponding bit of the result is taken from op0 or op1.
Or explained differently: it does what pick does on the operand level on the bit level.


merge(op op0) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 E1 E2 E3 1
Gold E0 1

merge(u mask, u bits0, u bits1) → op r0

operands: like Identity [xx:x]


encoding: merge(op op0) , exuArgs(op arg0, op arg1)

Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable