Difference between revisions of "Instruction Set/addss"

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{{DISPLAYTITLE:addss}}
 
{{DISPLAYTITLE:addss}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using saturating overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using saturating overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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'''aliases:''' addssv <br />
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'''aliases:''' addss2 <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#194|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addss|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#194|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addss|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#194|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addss|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#194|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addss|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#194|Decimal8]] || E0 E1 E2 E3 || 2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#194|Decimal16]] || E0 E1 E2 E3 || 2
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#195|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#addss|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#195|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#addss|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#195|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#addss|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#195|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#addss|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#195|Decimal8]] || E0 E1 E2 E3 || 2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#195|Decimal16]] || E0 E1 E2 E3 || 2
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:25, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using saturating overflow behavior   that produces condition codes

aliases: addss2
native on: all

Saturating signed integer addition. When a result value overflows or underflows for the width, it flats out at the biggest or smallest value respectively.

addss(s x, s y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

addss(s x, imm y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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