Difference between revisions of "Instruction Set/adduw"

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{{DISPLAYTITLE:adduw}}
 
{{DISPLAYTITLE:adduw}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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----
 
----
 
<code style="font-size:130%"><b style="color:#050">adduw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">adduw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]]
 
</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#205|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Tin/Encoding#adduw|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#205|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Copper/Encoding#adduw|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#205|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Silver/Encoding#adduw|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#205|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Gold/Encoding#adduw|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#205|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#205|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
 
|}
 
|}
  
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">adduw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#imm|imm]]</span> <span title="small immediate constant of per-slot varying range">y</span></i>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">adduw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#imm|imm]]</span> <span title="small immediate constant of per-slot varying range">y</span></i>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]]
 
</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#204|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Tin/Encoding#adduw|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#204|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Copper/Encoding#adduw|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#204|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Silver/Encoding#adduw|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#204|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
| [[Cores/Gold/Encoding#adduw|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#204|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#204|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:11, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening unsigned integer addition. When a result value overflows, it is widened.

adduw(u x, u y) → u r0

operands: like Widening xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

adduw(u x, imm y) → u r0

operands: like Widening xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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