Difference between revisions of "Instruction Set/shiftlsw"

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{{DISPLAYTITLE:shiftlsw}}
 
{{DISPLAYTITLE:shiftlsw}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
−
bitwise shift
+
Signed bitwise left shift. Widening.
 +
The bit count by which to shift is an unsigned number.
 +
The higher order bits get sign extended in the widening.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">shiftlsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">shiftlsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]]
 
</div>
 
</div>
 
<br />
 
<br />
Line 14:Line 17:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#shiftlsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Tin/Encoding#shiftlsw|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#shiftlsw|Copper]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Copper/Encoding#shiftlsw|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#shiftlsw|Silver]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Silver/Encoding#shiftlsw|Silver]] || E0 E1 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#shiftlsw|Gold]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Gold/Encoding#shiftlsw|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#shiftlsw|Decimal8]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#shiftlsw|Decimal16]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
 
|}
 
|}
  
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">shiftlsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#n|n]]</span> <span title="belt operand from ops window">bits</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">shiftlsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#n|n]]</span> <span title="belt operand from ops window">bits</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]]
 
</div>
 
</div>
 
<br />
 
<br />
Line 36:Line 35:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#shiftlsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Tin/Encoding#shiftlsw|Tin]] || E0 ||  
−
|-
+
−
| [[Cores/Copper/Encoding#shiftlsw|Copper]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
−
|-
+
−
| [[Cores/Silver/Encoding#shiftlsw|Silver]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#shiftlsw|Gold]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Copper/Encoding#shiftlsw|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#shiftlsw|Decimal8]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Silver/Encoding#shiftlsw|Silver]] || E0 E1 ||  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#shiftlsw|Decimal16]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Gold/Encoding#shiftlsw|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:10, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Signed bitwise left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get sign extended in the widening.

shiftlsw(s x, bit bits) → s r0

operands: like Widening xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1
Gold E0

shiftlsw(s x, n bits) → s r0

operands: like Widening xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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