Difference between revisions of "Instruction Set/mulufwfz"

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{{DISPLAYTITLE:mulufwfz}}
 
{{DISPLAYTITLE:mulufwfz}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned fixed point value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties away from zero]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned fixed point value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties away from zero]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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|-
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| [[Cores/Tin/Encoding#mulufwfz|Tin]] || E0 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Tin/Encoding#mulufwfz|Tin]] || E0 ||  
 
|-
 
|-
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| [[Cores/Copper/Encoding#mulufwfz|Copper]] || E0 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Copper/Encoding#mulufwfz|Copper]] || E0 ||  
 
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|-
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| [[Cores/Silver/Encoding#mulufwfz|Silver]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Silver/Encoding#mulufwfz|Silver]] || E0 E1 ||  
 
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|-
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| [[Cores/Gold/Encoding#mulufwfz|Gold]] || E0 E1 E2 E3 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Gold/Encoding#mulufwfz|Gold]] || E0 ||  
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|-
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| [[Cores/Decimal8/Encoding#mulufwfz|Decimal8]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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|-
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| [[Cores/Decimal16/Encoding#mulufwfz|Decimal16]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:09, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned fixed point value domain   using widening overflow behavior   that produces condition codes and rounds to nearest, ties away from zero

native on: all

Unsigned Fixed Point multiply. Rounds towards nearest away from zero. Widening.

mulufwfz(uf x, uf y, bit dot) → uf r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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