Difference between revisions of "Instruction Set/NaR"

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m (Protected "Instruction Set/NaR": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
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{{DISPLAYTITLE:NaR}}
 
{{DISPLAYTITLE:NaR}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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----
 
----
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<code style="font-size:130%"><b style="color:#050">NaR</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">NaR</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub>, [[Domains#op|op]] r<sub>1</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeDivRem|like DivRem [xx:xx]]]
 
</div>
 
</div>
 
<br />
 
<br />
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| [[Cores/Tin/Encoding#NaR|Tin]] || E0 || 1
 
| [[Cores/Tin/Encoding#NaR|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#NaR|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#NaR|Copper]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#NaR|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#NaR|Silver]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#NaR|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#NaR|Gold]] || E0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#NaR|Decimal8]] || E0 E1 E2 E3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#NaR|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
 
----
 
----
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<code style="font-size:130%"><b style="color:#050">NaR</b>(<i><span style="color:#009">[[Immediates#NaR|NaR]]</span> <span title="NaR kind">kind</span></i>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and scalarity (exu)">w</span></i>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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<code style="font-size:130%"><b style="color:#050">NaR</b>(<i><span style="color:#009">[[Immediates#NaR|NaR]]</span> <span title="NaR kind">NaR0</span></i>, )</code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoArgs|like NoArgs :[x]]]
 
</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#NaR|Tin]] || E0 || 1
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| [[Cores/Tin/Encoding#NaR|Tin]] || R0 R1 || 1
−
|-
+
−
| [[Cores/Copper/Encoding#NaR|Copper]] || E0 E1 || 1
+
−
|-
+
−
| [[Cores/Silver/Encoding#NaR|Silver]] || E0 E1 E2 E3 || 1
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#NaR|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Copper/Encoding#NaR|Copper]] || R0 R1 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#NaR|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#NaR|Silver]] || R0 R1 R2 R3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#NaR|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Gold/Encoding#NaR|Gold]] || R0 R1 || 1
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:07, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Produces a NaR of the given width and kind.

NaR(op x) → op r0, op r1

operands: like DivRem [xx:xx]


Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 1
Gold E0 1

NaR(NaR NaR0, )

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 1
Copper R0 R1 1
Silver R0 R1 R2 R3 1
Gold R0 R1 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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