Difference between revisions of "Instruction Set/f2sfe"
From Mill Computing Wiki
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{{DISPLAYTITLE:f2sfe}} | {{DISPLAYTITLE:f2sfe}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Overflow|using modulo overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Overflow|using modulo overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br /> |
| − | '''native on:''' [[Cores/Silver|Silver | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding#f2sfe|Silver]] || E0 E1 || | + | | [[Cores/Silver/Encoding#f2sfe|Silver]] || E0 E1 || rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5 |
| − | + | ||
| − | + | ||
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:02, 23 February 2021
speculable exu stream exu block compute phase operation in the binary floating point value domain using modulo overflow behavior that produces condition codes and rounds use current dynamic rounding mode
native on: Silver
Inexactly convert a binary floating point value to a signed integer, rounding toward even and normal modulo overflow.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
