Difference between revisions of "Instruction Set/addp"

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{{DISPLAYTITLE:addp}}
 
{{DISPLAYTITLE:addp}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the pointers value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the pointer value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
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addition
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Pointer addition. Protects the upper 4 reserved bits, can be scaled for indexing.
 +
 
 
----
 
----
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<code style="font-size:130%"><b style="color:#050">addp</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">y</span>, <i><span style="color:#009">[[Immediates#scale|scale]]</span> <span title="scale factor for indexes
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<code style="font-size:130%"><b style="color:#050">addp</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#imm|imm]]</span> <span title="small immediate constant of per-slot varying range">imm0</span></i>) &#8594; [[Domains#p|p]] r<sub>0</sub></code>
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            in load/store/lea">s</span></i>) &#8594; [[Domains#p|p]] r<sub>0</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeLea|like Lea px:p]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeAddp|like Addp [px:p]]]
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</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#192|Tin]] || E0 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
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| [[Cores/Tin/Encoding#addp|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#192|Copper]] || E0 E1 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
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| [[Cores/Copper/Encoding#addp|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#192|Silver]] || E0 E1 E2 E3 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
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| [[Cores/Silver/Encoding#addp|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
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| [[Cores/Gold/Encoding#192|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
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| [[Cores/Gold/Encoding#addp|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#192|Decimal8]] || E0 E1 E2 E3 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#192|Decimal16]] || E0 E1 E2 E3 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
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|}
 
|}
  
−
----
 
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<code style="font-size:130%"><b style="color:#050">addp</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#imm|imm]]</span> <span title="small immediate constant of per-slot varying range">y</span></i>, <i><span style="color:#009">[[Immediates#scale|scale]]</span> <span title="scale factor for indexes in load/store/lea">s</span></i>) &#8594; [[Domains#p|p]] r<sub>0</sub></code>
 
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeAddp|like Addp [px:p]]]
 
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</div>
 
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<br />
 
  
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
+
−
|-
+
−
| [[Cores/Tin/Encoding#193|Tin]] || E0 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
+
−
|-
+
−
| [[Cores/Copper/Encoding#193|Copper]] || E0 E1 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
+
−
|-
+
−
| [[Cores/Silver/Encoding#193|Silver]] || E0 E1 E2 E3 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
+
−
|-
+
−
| [[Cores/Gold/Encoding#193|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
+
−
|-
+
−
| [[Cores/Decimal8/Encoding#193|Decimal8]] || E0 E1 E2 E3 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#193|Decimal16]] || E0 E1 E2 E3 || d,b:d=1 d,h:d=1 d,w:d=1 d,d:d=2 d,q:d=2
+
−
|}
+

Latest revision as of 14:01, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the pointer value domain  

native on: all

Pointer addition. Protects the upper 4 reserved bits, can be scaled for indexing.

addp(p op0, imm imm0) → p r0

operands: like Lea px:p


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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