Difference between revisions of "Instruction Set/streamf"

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{{DISPLAYTITLE:streamf}}
 
{{DISPLAYTITLE:streamf}}
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|flow stream]]&nbsp;&nbsp;[[Decode|flow block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp;<br />
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|flow stream]]&nbsp;&nbsp;[[Decode|flow block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp;<br />
'''native on:''' [[Assembly|none]]<br />
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'''native on:''' [[Cores|all]]<br />
 
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
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|-
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| [[Cores/Tin/Encoding#streamf|Tin]] || F0 || 1
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|-
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| [[Cores/Copper/Encoding#streamf|Copper]] || F0 || 1
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|-
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| [[Cores/Silver/Encoding#streamf|Silver]] || F1 F2 || 1
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|-
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| [[Cores/Gold/Encoding#streamf|Gold]] || F0 || 1
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|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:57, 23 February 2021

realizing  flow stream  flow block  compute phase   operation  

native on: all

allocate streamer frame


streamf(lit rd_size, lit wr_size)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F1 F2 1
Gold F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable