Difference between revisions of "Instruction Set/streamf"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#845|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#streamf|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#845|Copper]] || F0 || 1
+
| [[Cores/Copper/Encoding#streamf|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#845|Silver]] || F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#streamf|Silver]] || F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#845|Gold]] || F0 F1 || 1
+
| [[Cores/Gold/Encoding#streamf|Gold]] || F0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#845|Decimal8]] || F1 F2 F3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#845|Decimal16]] || F1 F2 F3 || 1
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:57, 23 February 2021

realizing  flow stream  flow block  compute phase   operation  

native on: all

allocate streamer frame

streamf(lit rd_size, lit wr_size)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F1 F2 1
Gold F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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