Difference between revisions of "Instruction Set/f2ufe"

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{{DISPLAYTITLE:f2ufe}}
 
{{DISPLAYTITLE:f2ufe}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Overflow|using modulo overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties toward even adjacent value]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Overflow|using modulo overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br />
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'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
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'''native on:''' [[Cores/Silver|Silver]] <br />
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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|-
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| [[Cores/Silver/Encoding#f2ufe|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
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| [[Cores/Silver/Encoding#f2ufe|Silver]] || E0 E1 || rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5  
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|-
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| [[Cores/Gold/Encoding#f2ufe|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
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|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:57, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using modulo overflow behavior   that produces condition codes and rounds use current dynamic rounding mode

native on: Silver

Inexactly convert a binary floating point value to a unsigned integer, rounding toward even and normal modulo overflow.

f2ufe(f x) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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