Difference between revisions of "Instruction Set/countrtr"

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(Created page with "{{DISPLAYTITLE:countrtr}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu blo...")
 
 
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{{DISPLAYTITLE:countrtr}}
 
{{DISPLAYTITLE:countrtr}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
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number of bits before condition
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Count the one bits from the right.
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 +
<b>related operations:</b> [[Instruction_Set/countlfl|countlfl]], [[Instruction_Set/countltr|countltr]], [[Instruction_Set/countrfl|countrfl]]
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">countrtr</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">countrtr</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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<br />
 
<br />
  
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'''encoding:'''
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<code style="font-size:100%"><b style="color:#050">countrtr</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>)</code>
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<br />
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#246|Tin]] || E0 || 1
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| [[Cores/Tin/Encoding#countrtr|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#246|Copper]] || E0 || 1
+
| [[Cores/Copper/Encoding#countrtr|Copper]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#246|Silver]] || E0 || 1
+
| [[Cores/Silver/Encoding#countrtr|Silver]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#246|Gold]] || E0 || 1
+
| [[Cores/Gold/Encoding#countrtr|Gold]] || E0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#246|Decimal8]] || E0 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#246|Decimal16]] || E0 || 1
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:24, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

native on: all

Count the one bits from the right.

related operations: countlfl, countltr, countrfl

countrtr(op x) → op r0

operands: like Identity [xx:x]


encoding: countrtr(op x)

Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 1
Gold E0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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