Difference between revisions of "Instruction Set/subsw"
From Mill Computing Wiki
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{{DISPLAYTITLE:subsw}} | {{DISPLAYTITLE:subsw}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed integer value domain]] [[Overflow|using widening overflow behavior]] [[Condition Code|that produces condition codes]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
Revision as of 09:28, 9 February 2015
speculable exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
Widening signed integer subtraction. When a result value overflows, it is widened.
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
