Difference between revisions of "Instruction Set/shiftru"

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{{DISPLAYTITLE:shiftru}}
 
{{DISPLAYTITLE:shiftru}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>

Revision as of 09:24, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   that produces condition codes

native on: all

Unsigned bit shift right. Always fills in zeros to the highest order bits.

related operations: shiftl

shiftru(u x, bit bits) → u r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Copper E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Silver E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Gold E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal8 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal16 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2

shiftru(u x, n bits) → u r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Copper E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Silver E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Gold E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal8 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal16 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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