Difference between revisions of "Instruction Set/innertr0"

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(Created page with "{{DISPLAYTITLE:innertr0}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow b...")
 
 
(2 intermediate revisions by the same user not shown)
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</div>
 
</div>
  
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enter a loop
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Enter predicated loop with no result values on true.
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Everything that applies to [[Instruction_Set/inner0|inner0]] applies also here. The difference is the predicate to make it a conditional inner. And there is one less possible argument in all the encodings.
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<b>related operations:</b>  [[Instruction_Set/inner0|inner0]], [[Instruction_Set/innerfl0|innerfl0]]
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----
 
----
 
<code style="font-size:130%"><b style="color:#050">innertr0</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="call argument from calls window">q</span>, <span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from calls window">target</span>, <span style="color:#009">[[Domains#args|args]]</span> <span title="zero or more call  
 
<code style="font-size:130%"><b style="color:#050">innertr0</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="call argument from calls window">q</span>, <span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from calls window">target</span>, <span style="color:#009">[[Domains#args|args]]</span> <span title="zero or more call  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#1013|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innertr0|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1013|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innertr0|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1013|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innertr0|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
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| [[Cores/Gold/Encoding#1013|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#innertr0|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1013|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innertr0|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1013|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innertr0|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1014|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innertr0|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1014|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innertr0|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1014|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innertr0|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1014|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#innertr0|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1014|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innertr0|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1014|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innertr0|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 17:44, 4 February 2015

realizing  flow stream  flow block  call phase   operation  

native on: all

Enter predicated loop with no result values on true.

Everything that applies to inner0 applies also here. The difference is the predicate to make it a conditional inner. And there is one less possible argument in all the encodings.

related operations: inner0, innerfl0

innertr0(op q, p target, args args)

operands: like Inv :


encoding: innertr0(op q, p target, off argv, count argc) , innertr0(op q, p target, off argv, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

innertr0(op q, lbl target, args args)

operands: like Inv :


encoding: innertr0(op q, off target, count argc) , innertr0(op q, off target, count argc, lit argv) , innertr0(op q, off target, count argc, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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