Difference between revisions of "Instruction Set/narrowf"
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Revision as of 01:34, 3 January 2015
realizing exu stream exu block compute phase operation in the binary floating point value domain and rounds use current dynamic rounding mode
Half the width of a binary float value. Current rounding mode.
Can produce the IEEE 754 16bit binary float interchange format.
This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.
operands: like Narrowf [ff:½f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:h=3 d:w=4 q:d=5 |
| Gold | E0 E1 E2 E3 | w:h=3 d:w=4 q:d=5 |
operands: like Narrowvf [FF:½F]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5 |
| Gold | E0 E1 E2 E3 | wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
