Difference between revisions of "Instruction Set/cachebcl"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#cachebcl|Tin]] || F0 || 1 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#cachebcl|Copper]] || F0 || 1 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#cachebcl|Silver]] || F0 || 1 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#cachebcl|Gold]] || F0 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#cachebcl|Decimal8]] || F0 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#cachebcl|Decimal16]] || F0 || 1 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 01:30, 3 January 2015
cache control operation
operands: like Inv :
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 | 1 |
| Silver | F0 | 1 |
| Gold | F0 | 1 |
| Decimal8 | F0 | 1 |
| Decimal16 | F0 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
