Difference between revisions of "Instruction Set/cached"

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(Created page with "{{DISPLAYTITLE:cached}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow blo...")
 
m (Protected "Instruction Set/cached": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
(One intermediate revision by the same user not shown)
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#231|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#cached|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#231|Copper]] || F0 || 1
+
| [[Cores/Copper/Encoding#cached|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#231|Silver]] || F0 || 1
+
| [[Cores/Silver/Encoding#cached|Silver]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#231|Gold]] || F0 || 1
+
| [[Cores/Gold/Encoding#cached|Gold]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#231|Decimal8]] || F0 || 1
+
| [[Cores/Decimal8/Encoding#cached|Decimal8]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#231|Decimal16]] || F0 || 1
+
| [[Cores/Decimal16/Encoding#cached|Decimal16]] || F0 || 1
 
|}
 
|}
  
Line 37:Line 37:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#232|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#cached|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#232|Copper]] || F0 || 1
+
| [[Cores/Copper/Encoding#cached|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#232|Silver]] || F0 || 1
+
| [[Cores/Silver/Encoding#cached|Silver]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#232|Gold]] || F0 || 1
+
| [[Cores/Gold/Encoding#cached|Gold]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#232|Decimal8]] || F0 || 1
+
| [[Cores/Decimal8/Encoding#cached|Decimal8]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#232|Decimal16]] || F0 || 1
+
| [[Cores/Decimal16/Encoding#cached|Decimal16]] || F0 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 01:29, 3 January 2015

realizing  flow stream  flow block  compute phase   operation  

native on: all

cache control operation

cached(p lower, p upper)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 1
Gold F0 1
Decimal8 F0 1
Decimal16 F0 1

cached(p lower, p upper, p base)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 1
Gold F0 1
Decimal8 F0 1
Decimal16 F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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