Difference between revisions of "Instruction Set/narrowd"

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{{DISPLAYTITLE:narrowd}}
 
{{DISPLAYTITLE:narrowd}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Rounding|and rounds use current dynamic rounding mode]]<br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
</div>
 
</div>

Revision as of 18:52, 20 December 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   and rounds use current dynamic rounding mode

native on: Decimal8 Decimal16

narrow scalar to half width


narrowd(d v) → d r0

operands: like Narrowd [dd:½d]


Core In Slots Latencies
Decimal8 E0 E1 d:w=4 q:d=5
Decimal16 E0 E1 d:w=4 q:d=5

narrowd(d v1, d v2) → d r0

operands: like Narrowvd [DD:½D]


Core In Slots Latencies
Decimal8 E0 E1 dv,dv:wv=4 qv,qv:dv=5
Decimal16 E0 E1 dv,dv:wv=4 qv,qv:dv=5


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