Difference between revisions of "Instruction Set/integerfz"
From Mill Computing Wiki
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{{DISPLAYTITLE:integerfz}} | {{DISPLAYTITLE:integerfz}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Condition Code|that produces condition codes]]<br /> | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br /> |
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | '''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | ||
</div> | </div> | ||
| − | round to | + | Inexactly round a binary float to an integer valued float. Rounds towards zero. |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">integerfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">integerfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | ||
Revision as of 18:52, 20 December 2014
realizing exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes and rounds toward zero
Inexactly round a binary float to an integer valued float. Rounds towards zero.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
