Difference between revisions of "Instruction Set/f2uefx"
From Mill Computing Wiki
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:f2uefx}} | {{DISPLAYTITLE:f2uefx}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]]<br /> | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br /> |
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | '''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | ||
</div> | </div> | ||
Revision as of 18:51, 20 December 2014
realizing exu stream exu block compute phase operation in the binary floating point value domain using excepting overflow behavior that produces condition codes and rounds use current dynamic rounding mode
Exactly convert a binary floating point value to a unsigned integer, in current rounding mode and producing NaRs on overflow.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
