Difference between revisions of "Instruction Set/adduw"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#205|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Tin/Encoding#adduw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#205|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Copper/Encoding#adduw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#205|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Silver/Encoding#adduw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#205|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Gold/Encoding#adduw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#205|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#adduw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#205|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#adduw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|}
 
|}
  
Line 38:Line 38:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#204|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Tin/Encoding#adduw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#204|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Copper/Encoding#adduw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#204|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Silver/Encoding#adduw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#204|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Gold/Encoding#adduw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#204|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#adduw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#204|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#adduw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening unsigned integer addition. When a result value overflows, it is widened.

adduw(u x, u y) → u r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Copper E0 E1 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Silver E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal8 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal16 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2

adduw(u x, imm y) → u r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Copper E0 E1 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Silver E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal8 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal16 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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