Difference between revisions of "Instruction Set/narrowd"

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(Created page with "{{DISPLAYTITLE:narrowd}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bloc...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Decimal8/Encoding#642|Decimal8]] || E0 E1 || d:w=4 q:d=5  
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| [[Cores/Decimal8/Encoding#narrowd|Decimal8]] || E0 E1 || d:w=4 q:d=5  
 
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|-
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| [[Cores/Decimal16/Encoding#642|Decimal16]] || E0 E1 || d:w=4 q:d=5  
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| [[Cores/Decimal16/Encoding#narrowd|Decimal16]] || E0 E1 || d:w=4 q:d=5  
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Decimal8/Encoding#641|Decimal8]] || E0 E1 || dv,dv:wv=4 qv,qv:dv=5  
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| [[Cores/Decimal8/Encoding#narrowd|Decimal8]] || E0 E1 || dv,dv:wv=4 qv,qv:dv=5  
 
|-
 
|-
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| [[Cores/Decimal16/Encoding#641|Decimal16]] || E0 E1 || dv,dv:wv=4 qv,qv:dv=5  
+
| [[Cores/Decimal16/Encoding#narrowd|Decimal16]] || E0 E1 || dv,dv:wv=4 qv,qv:dv=5  
 
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|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain  

native on: Decimal8 Decimal16

narrow scalar to half width

narrowd(d v) → d r0

operands: like Narrowd [dd:½d]


Core In Slots Latencies
Decimal8 E0 E1 d:w=4 q:d=5
Decimal16 E0 E1 d:w=4 q:d=5

narrowd(d v1, d v2) → d r0

operands: like Narrowvd [DD:½D]


Core In Slots Latencies
Decimal8 E0 E1 dv,dv:wv=4 qv,qv:dv=5
Decimal16 E0 E1 dv,dv:wv=4 qv,qv:dv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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