Difference between revisions of "Instruction Set/retn"

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(Created page with "{{DISPLAYTITLE:retn}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|flowSkinny...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1168|Tin]] || f0 || 1
+
| [[Cores/Tin/Encoding#retn|Tin]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1168|Copper]] || f0 || 1
+
| [[Cores/Copper/Encoding#retn|Copper]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1168|Silver]] || f0 || 1
+
| [[Cores/Silver/Encoding#retn|Silver]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1168|Gold]] || f0 || 1
+
| [[Cores/Gold/Encoding#retn|Gold]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1168|Decimal8]] || f0 || 1
+
| [[Cores/Decimal8/Encoding#retn|Decimal8]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1168|Decimal16]] || f0 || 1
+
| [[Cores/Decimal16/Encoding#retn|Decimal16]] || f0 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1068|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#retn|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1068|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#retn|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1068|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#retn|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1068|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#retn|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1068|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#retn|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1068|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#retn|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
Line 73:Line 73:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1169|Tin]] || f0 || 1
+
| [[Cores/Tin/Encoding#retn|Tin]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1169|Copper]] || f0 || 1
+
| [[Cores/Copper/Encoding#retn|Copper]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1169|Silver]] || f0 || 1
+
| [[Cores/Silver/Encoding#retn|Silver]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1169|Gold]] || f1 || 1
+
| [[Cores/Gold/Encoding#retn|Gold]] || f1 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1169|Decimal8]] || f0 || 1
+
| [[Cores/Decimal8/Encoding#retn|Decimal8]] || f0 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1169|Decimal16]] || f0 || 1
+
| [[Cores/Decimal16/Encoding#retn|Decimal16]] || f0 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  flowSkinny block  transfer phase   operation  

native on: all

return from function

retn()

operands: like Inv :


alternate encoding: skinny

Core In Slots Latencies
Tin f0 1
Copper f0 1
Silver f0 1
Gold f0 1
Decimal8 f0 1
Decimal16 f0 1

retn(ops vs) → ops r0 ...

operands: like Inv :


encoding: retn(off vs, count c) , retn(off vs, count c, lit vs) , retn(off vs, count c, lit vs, lit vs) , retn(off vs, count c, lit vs, lit vs, lit vs)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

retn(op v) → op r0

operands: like Inv :


alternate encoding: skinny

Core In Slots Latencies
Tin f0 1
Copper f0 1
Silver f0 1
Gold f1 1
Decimal8 f0 1
Decimal16 f0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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