Difference between revisions of "Instruction Set/lssp"

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(Created page with "{{DISPLAYTITLE:lssp}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#557|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#lssp|Tin]] || E0 || 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#557|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#lssp|Copper]] || E0 E1 || 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#557|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#lssp|Silver]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#557|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#lssp|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#557|Decimal8]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal8/Encoding#lssp|Decimal8]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#557|Decimal16]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal16/Encoding#lssp|Decimal16]] || E0 E1 E2 E3 || 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the pointers value domain  

aliases: gtrp
native on: all

less than

lssp(p x, p y) → p r0

operands: like Eqlp pp:p


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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