Difference between revisions of "Instruction Set/store"

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(Created page with "{{DISPLAYTITLE:store}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow bloc...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#828|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#828|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#828|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#828|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#828|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#store|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#828|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#store|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
Line 37:Line 37:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#829|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#829|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#829|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#829|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#829|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#store|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#829|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#store|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
Line 60:Line 60:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#827|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#827|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#827|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#827|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#827|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#store|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#827|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#store|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
Line 82:Line 82:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#826|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#826|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#826|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#826|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#826|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#store|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#826|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#store|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
Line 105:Line 105:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#825|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#store|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#825|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#store|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#825|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#store|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#825|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#store|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#825|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#store|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#825|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#store|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  flow stream  flow block  writer phase   operation   in the logical value domain  

native on: all

store to memory

store(base b, off o, s i, scale s, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

store(base b, off o, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

store(p b, off o, s i, scale s, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

store(p b, off o, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

store(p b, op v, memAttr m)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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