Difference between revisions of "Instruction Set/cachebdl"

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(Created page with "{{DISPLAYTITLE:cachebdl}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow b...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#230|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#cachebdl|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#230|Copper]] || F0 || 1
+
| [[Cores/Copper/Encoding#cachebdl|Copper]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#230|Silver]] || F0 || 1
+
| [[Cores/Silver/Encoding#cachebdl|Silver]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#230|Gold]] || F0 || 1
+
| [[Cores/Gold/Encoding#cachebdl|Gold]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#230|Decimal8]] || F0 || 1
+
| [[Cores/Decimal8/Encoding#cachebdl|Decimal8]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#230|Decimal16]] || F0 || 1
+
| [[Cores/Decimal16/Encoding#cachebdl|Decimal16]] || F0 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  flow stream  flow block  compute phase   operation  

native on: all

cache control operation

cachebdl(p lower, p upper)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 1
Gold F0 1
Decimal8 F0 1
Decimal16 F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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