Difference between revisions of "Instruction Set/eql"

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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#271|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#eql|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#271|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#eql|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#271|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#eql|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#271|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#eql|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#271|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#eql|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#271|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#eql|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
Line 38:Line 38:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#273|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#eql|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#273|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#eql|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#273|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#eql|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#273|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#eql|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#273|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#eql|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#273|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#eql|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">eql</b>(<span style="color:#666">conditioncode</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">eql</b>([[Condition_Code|<span style="color:#666">conditioncode</span>]]) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
</div>
 
</div>
−
Gets the equality condition code of the ganged operation and puts it on the belt.<br />
+
Gets the inequality condition code of the ganged operation and puts it on the belt.
 +
<b>related operations:</b> [[Instruction_Set/neq|neq]], [[Instruction_Set/gtr|gtr]], [[Instruction_Set/geq|geq]], [[Instruction_Set/lss|lss]], [[Instruction_Set/leq|leq]], [[Instruction_Set/carry|carry]], [[Instruction_Set/overflows|overflows]], [[Instruction_Set/fault|fault]]
 +
<br />
  
 
'''alternate encoding:''' [[Encoding#Skinny|skinny]]
 
'''alternate encoding:''' [[Encoding#Skinny|skinny]]
Line 61:Line 63:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#272|Tin]] || e0 E0 E1 || 1
+
| [[Cores/Tin/Encoding#eql|Tin]] || e0 E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#272|Copper]] || e0 E0 E1 || 1
+
| [[Cores/Copper/Encoding#eql|Copper]] || e0 E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#272|Silver]] || e0 E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#eql|Silver]] || e0 E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#272|Gold]] || e0 E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#eql|Gold]] || e0 E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#272|Decimal8]] || e0 E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#eql|Decimal8]] || e0 E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#272|Decimal16]] || e0 E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#eql|Decimal16]] || e0 E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

aliases: eqls eqlu
native on: all

Integer equality.

eql(op x, op y) → op r0

operands: like Identity [xx:x]

Both operands must be the same byte size.

Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

eql(op x, imm y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

eql(conditioncode) → op r0

operands: like Identity [xx:x]

Gets the inequality condition code of the ganged operation and puts it on the belt. related operations: neq, gtr, geq, lss, leq, carry, overflows, fault

alternate encoding: skinny

Core In Slots Latencies
Tin e0 E0 E1 1
Copper e0 E0 E1 1
Silver e0 E0 E1 E2 E3 1
Gold e0 E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 e0 E0 E1 E2 E3 1
Decimal16 e0 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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