Difference between revisions of "Instruction Set/adduwv"
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− | addition | + | Widening unsigned integer vector addition. |
+ | If any of the result values in the vector overflows, the vector is widened as with [[Instruction_Set/widenuv|widenuv]]. | ||
+ | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">adduwv</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#u|u]] r<sub>0</sub>, [[Domains#u|u]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">adduwv</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#u|u]] r<sub>0</sub>, [[Domains#u|u]] r<sub>1</sub></code> |
Revision as of 10:16, 12 November 2014
realizing exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
Widening unsigned integer vector addition. If any of the result values in the vector overflows, the vector is widened as with widenuv.
operands: like Widenv XX:2X2X
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | 2 2 |
Copper | E0 E1 | 2 2 |
Silver | E0 E1 E2 E3 | 2 2 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
Decimal8 | E0 E1 E2 E3 | 2 2 |
Decimal16 | E0 E1 E2 E3 | 2 2 |
adduwv(u x, imm y) → u r0, u r1
operands: like Widenv XX:2X2X
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | 2 2 |
Copper | E0 E1 | 2 2 |
Silver | E0 E1 E2 E3 | 2 2 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
Decimal8 | E0 E1 E2 E3 | 2 2 |
Decimal16 | E0 E1 E2 E3 | 2 2 |