Will_Edwards

the compiler is responsible for coming up with bundles of operations which
can be executed concurrently.

Correct.

How do you know the compiler can always come up with bundles
which have 30 parallel operations ?

Always is a strong word; we obviously can’t. The conventional wisdom was that there’s only an ILP of 2 or so in open code. This is not true. Our Execution talk describes phasing which is one of the ways we improve on this.

You answer your own question very well 🙂 I think your reasoning closely approximates the ootb team.

> Or maybe you all have thought of some clever means of partitioning your belt network by depth that isn’t obvious to me (and so is probably NYF), or I’m wrong to thinkg that all inputs and outputs have to have the same size?

Well holistically Mill is an ABI at the load module level. But its very much grounded in a hardware architecture, of course. Yet how the belt is implemented is always described in the talks as an implementation detail…

Do you have any insights into how to do this or how you imagine it working?

Can mods (like myself) host images on ootbcomp? WP normally has add-media dialogs, but I cannot find them for ootbcomp.com.

Do the 4th and 5th level replies have the same indent in your browser?

We seem to quickly get more than 5 deep in a thread and then it becomes really hard to follow. I just answered a couple of questions only to later work out that Ivan had answered them in his usual depth and detail..

Yes, you can use the stack to pass arguments between frames.

You may also use the heap. And how you do it depends a lot on whether you make a distinction between objects and primitives, and how you do garbage collection.

Normal calls within a compilation unit are very conventional and all the normal approaches work; its only if you want to take advantage of the Mill protection mechanism or its convenient for dynamic linking that you use portals.

Answering particular parts of your question where I can:

> Wow much of the selection of the current phasing setup was a result of the way the hardware works, and how much profiling actual code to see what would be useful in practice?

Well, definitely informed by code analysis. There’s an upcoming talk on Configuration, and its been described in the talks and in the Hackaday interview.

A central tenet of the Mill is that people building products can prototype custom processor specifications in the simulator very quickly and choose a configuration with the best power performance tradeoff informed by benchmarking representative code.

> With regard to calls, how many cycles do they normally take in overhead?

One. Calls and branches (that are correctly predicted) transfer already in the next cycle. In the case of mis-predictions where the destination is in the instruction cache, again the Mill is unusually fast; it has a penalty of just five or so cycles.

Additionally, there is is none of the conventional pre- and post-ambles.

Yes, I understand you.

We do want to produce an early “make” model for enthusiasts, as there are lots of enthusiasts who have asked for Mill dev boards. The funding mechanics priority and timescales of this is still being discussed.

Does the mill support (arbitrary) vector element swizzling?

Yes. There is a shuffle op for arbitrary rearrangements of a vector.

I’m just wondering if the same functionality that enables free pick might also allow free swizzles.

I believe its in the op phase.

I could see how it might be machine dependent due to different vector sizes.

Well, you can always use the remainder op to create a mask that you then pick against with 0s or Nones to create a partially filled vector? This was covered in the strcpy example in the Metadata talk and the Introduction to the Mill CPU Programming Model post.

True, the analogy doesn’t stand up to such scrutiny 🙂

Your compiler is still responsible for Tail-Call-Optimisation to turn recursion into loops. The CPU does what it’s told.

Well, it would be staggeringly unlikely to be a meaningful program because the two streams diverge in memory from the entry point; another address e.g. EBB+n would mean that the bit stream fragment between EBB…EBB+n that is one side is also valid instructions to the other side when decoded backwards…

Of course, trying to generate two legal, overlapping EBBs with this property may be a fun exercise for determined readers 🙂

Add-reductions keep coming up in my mind when doing 3D (e.g. as game and graphics engines will be doing buckets of). In 3D graphics there are lots of vectors which are 3 or 4 long.

I imagine that, whilst belt vectors are powers-of-2 in length, you can load a non-power-of-2 vector, and the load automatically pads it with Nones? So if you load(addr,float32,3) you actually get xyzNone.

And you’d want an add reduction to treat Nones as 0 rather than propogate them.

The shuffle sounds useful for computing cross-product.

Generally in games/graphics you want sqrt, inverse sqrt and dot product. You also likely want to sum a vector again when you do matrix multiplication.

My thinking would be that in the Mill IR sqrt, inverse sqrt, sum reduction, fork/exec/vfork, memcpy and memmove etc are built-in functions, and the specialiser on each target turns that into single or multiple operations as the target supports. So that’s like microcode (or standard function inlining), but in the specialising compiler rather than in the outer compiler or on-CPU. It would be a hassle for a specialiser to have to unravel some old IR that is coding its own sqrt loop using a lower-level operation if there is ever hardware with better built-in sqrt, for example?

And as for hazards, we all want to avoid them, but pragmatically if its the specialiser that has to know about them and it has to know about one of them, it might as well open the floodgates and have a few more 😉