Forum Replies Created
- Paul A. ClaytonParticipantFebruary 17, 2016 at 10:50 amPost count: 2
If there is any problem, it will be in the memory hierarchy and the protection model when a Mill and another core are on the same chip and share address space. The Mill separates protection from paging and protects at byte granularity. Consequently it would not be possible for a Mill and an ARM (say) to safely share a 17-byte buffer, while two Mills can do so. The Mill also supports backless memory that has no allocated pages, which is impossible on a core where paging is in front of the caches. Consequently any memory shared between Mill and non-Mill would have to have real DRAM allocated for it. All these issues can be handled in software, but would have to be addressed.
While not an ideal solution, an approximation of fine-grained protection could be implemented on the Mill side by only communicating data that is readable by the alien architecture and ignoring/filtering out writes. Given that the alien architecture would not communicate what protection domain (“turf”) is accessing the memory, such protection would have to be system-wide.
Likewise backless memory is not a problem because the alien architecture’s memory system could be given shadow page addresses which it would treat as physical addresses while the Mill component (and memory controllers) would treat as virtual addresses. (“All problems in computer science can be solved by another level of indirection.”)
A similarly painful hardware problem might occur with concurrency control. The Mill uses optimistic concurrency control, and should have no problem working with cores that also do so: PowerPC, M68k, z-series. However, cores that use bus locking for concurrency might have trouble. At a guess, you’d probably have assertion of a bus lock cause a bust of any in-flight Mill transaction. Going the other way, I suppose you could have the bus locked for the duration of an active transaction. Both of these would have a lot of spurious interference; it that was enough of a problem then you’d need more hardware smarts to do the integration.
Implementing a conceptual bus lock as an actual bus lock seems quite suboptimal (substantially limiting parallelism). (“As if” is an important concept.)
For the Mill, I suspect that alien ISAs (other than different Mill specializations) on the same chip would be limited more specialized processing or extremely low power, performance, and area. In neither case is an SMP communication model likely to be used.