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  • milljma
    Participant
    Post count: 3
    in reply to: Compiler #747

    If you give me a sequence of 30 Sparc instructions like that shown in slide 26, I can
    execute them all in one cycle. There is nothing about a belt or phasing that cannot be
    done in an implementation of an existing an ISA, such as Sparc. Your compiler is the key
    to your performance advantage.

    My unsolicited ( & probably unwelcome ) suggestion is
    1. Use the open source Sparc compiler & RTL as a base to implement your key ideas. You can even extend the ISA with your favorite instructions.

    2. Demonstrate performance advantage with some existing Sparc code. Limitations are acceptable.

    If you can do this, Oracle will fund you & also buy you out once you finish the whole
    thing. So your funding & exit considerations are all taken care of.

    Nobody cares about an extra 100K or even 500K gates. It’s a non issue. If your compiler
    can extract large ILP from loops, slide 26, then concurrent execution can be done. There
    is no gate count limit & gates are blazingly fast now days.

  • milljma
    Participant
    Post count: 3
    in reply to: Compiler #745

    I’ve looked at your execution slides. Is slide 26 the kind of situation you’re talking
    about when you say ILP is more than 2 ? Isn’t it also very common to have a lot of
    logical branch/decision making in a program ? Are slides 45 & 48 your answer to branching ? Do you have a compiler ? If so, have you tested it to verify average ILP of
    more than 4 ?

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