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  • jabowery
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    Post count: 6
    in reply to: Transistor counts? #3697

    Algorithmic information is the shortest program that outputs a given set of data. Searching for that algorithmic information requires a universal Turing machine equivalent upon which to run that program. There’s no escaping the universality requirement for algorithmic information search. Moreover, scientific induction can’t do better than algorithmic information, which is why its the proper basis for ML.

    Energy constrains the economics of proof-of-work.

    • This reply was modified 6 days, 8 hours ago by  jabowery.
  • jabowery
    Participant
    Post count: 6
    in reply to: Transistor counts? #3695

    Choice of mining hardware depends on the choice of proof-of-work algorithm. As the guy who came up with the idea for The Hutter Prize for Lossless Compression of Human Knowledge clear back in 2005, I’m rather distressed at the direction taken by the machine learning industry which elides the algorithmic information theoretic foundations. I convinced the mining chip executive that the ML industry’s foundation in matrix multiplication needs to be replaced with algorithmic information search. Automacoin is somewhat related to the direction I’d like to see the mining industry take.

  • jabowery
    Participant
    Post count: 6
    in reply to: Transistor counts? #3693

    My motivation for asking is that I just returned from Bitcoin 2021 in Miami where I met up with an executive with a mining chip manufacturer. Elon Musk’s May 12 tweet about exhorbitant cryptocurrency energy usage caused a quarter trillion dollar loss of market capitalization to Bitcoin alone. I wanted to explore alternative proof-of-work algorithms based on Mill architecture in a IRAM chip featuring a large number of cores, but had no idea how to estimate how much real estate it would take to achieve given levels of performance.

  • jabowery
    Participant
    Post count: 6
    in reply to: Memory #516

    Using real estate for more cores in preference to threading, resulting from the the Mill’s other architectural features, brings to mind a question about on-chip memory architecture that, while of no immediate consequence to the Mill chip, might affect future trade offs in real estate use.

    With 14nm and higher density technologies coming on line, there is a point where it makes sense prefer on-chip shared memory to some other uses of real estate. This raises the problem of increasing latency to on-chip memory, not only with size of the memory but with the number of cores sharing it. In particular, it seems that with an increasing number of cores, a critical problem is reducing arbitration time among cores for shared, interleaved, on-chip memory banks. In this case, interleaving isn’t to allow a given core to issue a large number of memory accesses in rapid succession despite high latency; it is to service a large number of cores — all with low latency.

    Toward that end I came up with a circuit that does the arbitration in analog which, if it works when scaled down to 14nm and GHz frequencies, might result in a architectural preference for a on-chip cross-bar switch between interleaved low-latency memory banks and a relatively large numbers of cores.

    This spans disciplines — a problem well known to folks involved with the Mill architecture which spans disciplines between software and computer architecture (rather than between computer architecture and analog electronics).

    I’d appreciate any feedback from folks who understand the difficulty of cross-disciplinary technology and have a better grasp the issues than do I.

  • jabowery
    Participant
    Post count: 6
    in reply to: Memory #519

    Thank you for pointing out the challenge of routing latency. Rather than further digression from the Mill memory architecture here, can you suggest a proper forum for discussing this?

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