Ghadi

A new paper from DJB and others, thought it may be interesting to this forum.

BasicBlocker: Redesigning ISAs to Eliminate Speculative-Execution Attacks

More Spectre like exploits — this one seems particularly serious:

https://eprint.iacr.org/2018/1060

Simultaneous Multithreading (SMT) architectures are attractive targets for side-channel enabled attackers, with their inherently broader attack surface that exposes more per physical core microarchitecture components than cross-core attacks. In this work, we explore SMT execution engine sharing as a side-channel leakage source. We target ports to stacks of execution units to create a high-resolution timing side-channel due to port contention, inherently stealthy since it does not depend on the memory subsystem like other cache or TLB based attacks. Implementing said channel on Intel Skylake and Kaby Lake architectures featuring Hyper-Threading, we mount and end-to-end attack that recovers a P-384 private key from an OpenSSL-powered TLS server using a small number of repeated TLS handshake attempts. Furthermore, we show that traces targeting shared libraries, static builds, and SGX enclaves are essentially identical, hence our channel has wide target application.

How does this intersect with the Mill?

I’m very excited to see how to implement an interpreter minus megamorphic dispatch. Is the talk from Wednesday available somewhere?

Does this also relate to how lightweight coroutines a la Golang are handled in a branch-prediction-friendly style? (Similar issue with fork/join style work-stealing)