Mill Computing, Inc. Forums The Mill Architecture Carryless multiply

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  • Validark
    Participant
    Post count: 20
    #3852 |

    Does the Mill have an instruction for carryless multiply? It’s pretty good for certain hash algorithms, but it’s also used for the “prefix xor” operation. This operation needs to be able to do a carryless multiply by all one’s (i.e. -1) and is used in high performance SIMD libraries like simdjson. Please check the link for more details.

  • Ivan Godard
    Keymaster
    Post count: 689

    There’s no such instruction,and in general the base ISA avoids such specialized usage. Nothing prevents adding it to an FU and that FU to particular specialized member; you’d get at it via an intrinsic. The auto-generated include files have definitions of intrinsics for all instructions in the target, and the specializer schedules them into the correct slots.

    However, I suspect that anyone adding operations for such a purpose would add a more general Galois product. That would be straightforward for {b*b}[d], i.e. two byte values and a 64-bit rule. Where it gets harder in hardware is for larger arguments and correspondingly larger rules – {8*8}[4096] for example. Then you have tough problems with dynamically specifying the rule, and what to do if different processes both want to use the hardware with different rules and … So the base architecture stays out, and lets the customer with specific needs decide what they want and pay the NRE.

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