Mill Computing, Inc. Forums The Mill Implementation Any plans for 2024?

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  • Validark
    Participant
    Post count: 21
    #3987 |

    This year I’ve been attending programming meetups fairly regularly and I’ve heard people express that they want x86-64 to die, or that it’s too power hungry, and many hope it gets replaced by some RISC architecture that still needs to be an out-of-order superscalar to be fast. (And a lot of people online seem to think you never need microcode on RISC architectures?)

    Don’t get me wrong, ARM is cool and there are a number of things I like about it. RISC-V seems interesting too. But I’m saddened that these architectural swaps are not fundamental improvements but primarily imply a simplification of the decoder phase and a reduction of historical artifacts; which by the way, Intel already hopes/plans to remove via x86S. Of course there are other differences like different takes on SIMD/SWAR, different memory models, and differences in what can be done in one instruction vs many, but at the end of the day, I believe they’re all roughly in the same category. They all need a lot of heroics that take a lot of die space and electricity to go fast.

    But I don’t want yet another out-of-order superscalar architecture. Well, I do for my next laptop, because it’s my only choice if I want great performance today. But ultimately, I want a radical departure from conventional CPUs. I want to own a Mill computer, even if the first one isn’t the best or doesn’t guarantee backwards compatibility. What needs to be done to get there?

    There’s so much hunger for better ISAs with better power efficiency, and I know we could do better than just switching to ARM and RISC-V. When can we see more from the Mill? Could we maybe get an initiative going for a new website, new videos (even just remakes?), maybe make some TikToks/Reels/Shorts? I don’t want the Mill to be left out of the ISA wars.

    Thank you.

  • Art
    Participant
    Post count: 10

    We would love to be selling Mill computers also.

    What needs to happen to get there: The investment of money to hire the skilled people needed to accelerate Mill development. It’s that simple and not a new need. Likely $12M USD over a 2 to 3 year period to some initial form of production silicon.

    Accelerating development will require some additional C++ developers familiar with a range of topics from micro-kernels to Posix libraries to C/C++ libraries to LLVM backend code generation, as well as developers familiar with both C++ and System Verilog as it applies to FPGA and ASIC usage. With more people we could also spare the time to refresh the website, do new videos, etc. When we did the videos some years ago it resulted in enough investment to file patents, but not much more. The result was we had patents, which we needed after the patent law changes, but the video production effort took time away from key parts of development.

    We are working on various approaches to securing the investment needed.

    In the meantime, we have a few people who are continuing on with development, and we are in no immediate danger of failing. We are to the point we can run thousands of test programs, as well as Coremark, on our internal cycle accurate instruction set simulator. While the scope of what we can compile and run still needs to be expanded, what we have so far indicates the Mill Architecture’s viability.

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