A New ISA – VISC (Variable Instruction set Computing)

There’s been quite a bit of marketing around Soft Machines, but a dearth of “how it works” technical content. Some patents are beginning to show up, but so far nothing on the critical part: the thread cracker. Everybody and his brother claims that they can split a conventional thread into independent threads (of some granularity) and run them on independent cores. Nobody has succeeded except in carefully chosen test cases that show embarrassing parallelism already; if your app is loop-heavy, the iterations are independent, and the work in one iteration is complicated enough to justify the cost of migrating the cracked thread’s pieces to another core – then a system like Soft Machines should work just fine. Such loads are common in HPC – and rare elsewhere.

I’d be delighted if Soft can get it to work. But I’d like to see it work, or a paper describing how the cracker works in enough detail to evaluate from first principles, like we have done for the Mill.

I have seen nothing so far.