Mill Computing, Inc. › Forums › The Mill › Architecture › 40/80-bit computing
- AuthorPosts
- #4025 |
What are some difficulties in implementing a fully 40/80-bit computer (i.e., not supporting 32-bit, 64-bit word sizes)?
I realize that this could be trivial to do if one could be permitted to use word addressing instead of byte-level addressing in the computer; but, given that much of the code on github assumes that the architecture will use byte addressing, do you think it’s possible that a move could be made to this new type of architecture?
The difficulty, I think, lies in the fact that there needs to be a correspondence between the cache size and word size (such that one is divisible by the other); the page size needs to be divisible by both, as well. Page sizes have to be power-of-2 based so that simple bit-wise indexing can be used to find the nearest page when doing TLB stuff.
I have a vested interest in this, as I am working with audio/computer music/synthesis.
This would have a severe impact on address computation for indexed loads.
There are likely other problems with non-power of 2 sized words, but just the difficulty with indexed loads is sufficient to rule out 40/80 bit word sizes. Bit aligning and masking an index is trivial compared to the integer multiplication required to be part of the indexed load instruction with those word sizes.
- AuthorPosts
You must be logged in to reply to this topic.