Mill Computing, Inc. Forums The Mill Architecture Security Reply To: Security

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It may have been obvious to others, but it’s only just “clicked” for me what is meant by an “external interface”. My assumption was something like an external PCIe card performing some accelerating functionality.

If my “click” is correct, then a better view would be like an ADC on an embedded microcontroller. It’s still part of the chip, but it’s not accessed with a “readadc” opcode, it’s accessed by setting the ADSC bit in the ADCSRA register, then reading ADC register at some point in the future (atmel AVR example)

So instead of a RdRand opcode like x64, you could have something like (paraphrasing, not certain of the syntax) …


… and if the RNG takes more time than you expected to provide the data, then you stall, and that’s ok, because loads are designed to handle stalls. That doesn’t mean that you’ll have a 300 cycle latency to get a random number, but it does mean the RNG is allowed to be flexible on its timing.

Is my understanding correct?