Mill Computing, Inc. › Forums › The Mill › Architecture › Introduction to the Mill CPU Programming Model › Reply To: Introduction to the Mill CPU Programming Model
February 8, 2014 at 8:09 am
Post count: 4
What can you change in CPU design to reduce memory bandwidth issues? Would you be able to, say, have 4 or 6 memory channels instead of the 2 typical today?
Given the memory bandwidth limitations and the fact that Mill can pipeline AND vectorize loops, wouldn’t trading a bit of latency help throughput on these very short loops?