Reply To: SIMS architecture

Hardware pipe-line

The pipe-line stages are as follows: fetch, decode, virtual stream assignment, operation, memory, write-back.

Nested streaming

It is not possible to nest a SIMS streaming context within another context, if the inner context is conditional. Nevertheless, it would be prudent to permit nested for loops to be ‘streamed’, granting a significant increase in performance. Using a bizarre technique called ‘outlining’ to remove a loop code block and place it into a separate function body, it is possible to emulate streaming on nested loops when the inner loop is conditional.

Software pipe-lining

SIMS supports pipe-lining and uses manual register rotation, but it is not necessary to encode a prologue or epilogue; instead, one of two techniques might be used to mask instructions that would otherwise function within prologue/epilogue: the first involves simple instruction masking, the other involves side-effect masking using tagged values that indicate whether state should be modified.

Stackless programming with cached register rotation

It is not necessary to write register values to the stack when running out of registers; instead, the CPU can stream register values to and from a register caching system (which itself can dynamically stream to and from RAM); in addition, these cached values can be properly rotated as necessary to support software pipe-lining. Lastly, the floating-point padding bits normally found in registers can be cached along with register values.

Virtual static scheduling

VLIW is not used in SIMS. The compiler emits a static schedule, and the CPU is expected to conform to the semantics laid out in this schedule; however, the CPU can dynamically assign fewer or more functional units to virtual compute units, if needed.