Reply To: Memory level parallelism and HW scouts

Maybe it was poorly worded. What I meant was that an OoO could find a way to overlap stalls where static instruction bundles could not.

Suppose the scheduling is `load_offset(a, i, delay), load_offset(b, j, delay);
…
// a[i], b[j] drop
con(member_offset), load_offset(b0, b2, delay), load_offset(b1, b2, delay);`

Imagine a[i] hits but b[j] misses, now we have no choice but to stall. Then imagine a[i]->member misses but b[j]->member hits, now we have no choice but to stall again. Whereas an OoO processor can see that a[i] hits and issue the load for a[i]->member before retiring the load for b[j].