Mill Computing, Inc. Forums The Mill Architecture Carryless multiply Reply To: Carryless multiply

Ivan Godard
Post count: 689

There’s no such instruction,and in general the base ISA avoids such specialized usage. Nothing prevents adding it to an FU and that FU to particular specialized member; you’d get at it via an intrinsic. The auto-generated include files have definitions of intrinsics for all instructions in the target, and the specializer schedules them into the correct slots.

However, I suspect that anyone adding operations for such a purpose would add a more general Galois product. That would be straightforward for {b*b}[d], i.e. two byte values and a 64-bit rule. Where it gets harder in hardware is for larger arguments and correspondingly larger rules – {8*8}[4096] for example. Then you have tough problems with dynamically specifying the rule, and what to do if different processes both want to use the hardware with different rules and … So the base architecture stays out, and lets the customer with specific needs decide what they want and pay the NRE.