Earlier posts about some of the things you mention:
“We don’t do SMT.”.
I think it has also been said as an answer at a Q&A session after a talk (?) that all multi-core Mills will be single-chip designs sharing the same cache.
Synchronisation primitives (such as those used for buffers for producer/consumer threads) are notoriously difficult to make right. As on any platform, those would be best left to the guys writing standard libraries I think.
A little has been said about synchronisation on The Mill though:
multi-cpu memory model
How to schedule communicating threads and when to move threads between cores is a question for operating system designers, I think. I would be surprised if that is significantly different on the Mill than on any other architecture.
- This reply was modified 1 year, 7 months ago by Findecanor.