Mill Computing, Inc. Forums The Mill Architecture multi-cpu memory model Reply To: multi-cpu memory model

Ivan Godard
Keymaster
Post count: 627

Those ops support the Mill’s optimistic concurrency model, essentially a bounded hardware transaction memory (HTM). Google for it 🙂 You can use them to implement pessimistic locking primitives like compare-and-swap (CAS), but will lose the gain available if you used transactions instead.

I think the instructions you sorta remember were a description of the semantics of transactions as implemented in the hardware. The ones in the ISA in the Wiki provide the bounds of the transaction; they work in conjunction with loads and stores that are marked are transaction participants. The sequence is enter -> some loads and stores -> exit, and the changes between enter and exit happen all-or-none atomically.