Mill Computing, Inc. Forums The Mill Architecture multi-cpu memory model Reply To: multi-cpu memory model

CPUSpeedup
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Post count: 8

I’d like to know the opening thread answer and I’d like to ask a follow up question about the atomic model. I remember in a video there seemed to be an instruction to watch a memory address which you pair with a store. I think the store returns a bool saying if it succeeded or not? and it may fail if another core (or another store?) writes to that memory address? Perhaps I remember wrong. It was suppose to allow us to build primitives like a compare and swap?

However in the wiki I see enterAtomic/exitAtomic/abortAtomic http://millcomputing.com/wiki/Instruction_Set/enterAtomic I guess the instructions I once saw no longer exit?

  • This reply was modified 2 years, 1 month ago by  CPUSpeedup.